library ieee;
use ieee.std_logic_1164.all;


ENTITY LRshift is

PORT (clock, reset, enable, left_shift, firstentry: IN STD_LOGIC;
      output, shifted_value: OUT STD_LOGIC_VECTOR(31 downto 0)
);
END LRshift;                                                         
                                             
architecture structural of LRshift is

component snakes IS
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		enable		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
END component;

component shift IS
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		direction		: IN STD_LOGIC ;
		distance		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
END component;

component shift_mux IS
	PORT
	(
		data0x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		data1x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		sel		: IN STD_LOGIC ;
		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
END component;

signal chosen_data, shifted_data, output_buffer: STD_LOGIC_VECTOR(31 downto 0);

begin

reg: snakes port map(reset, clock, chosen_data, enable, output_buffer);
leftright: shift port map(output_buffer, left_shift, '1', shifted_data); 
mux: shift_mux port map(shifted_data, "10000000000000000000000000000000", firstentry, chosen_data); 
output<= output_buffer;
shifted_value<= shifted_data;

end structural;   